The present invention relates to a semiconductor integrated circuit device and, more particularly, to a technology which is effective when applied to a semiconductor integrated circuit device including a buffer circuit and an internal circuit having a complementary MISFET.
There has been developed the ASIC (as abbreviated from Application Specific Integrated Circuit). The ASIC is generally arranged with an internal circuit such as a logic circuit or a memory circuit at the central region of the circuit packaging plane of a semiconductor substrate. In the peripheral region of the circuit packaging plane of the aforementioned semiconductor substrate, there is arranged a buffer circuit which is used as an interface circuit for an internal device. The peripheral region of the buffer circuit is further arranged with external terminals (or bonding pads).
The aforementioned ASIC has its internal circuit arranged in a matrix form with a plurality or basic cells as the minimum functional block unit for repetitions and further with a circuit which is composed of the basic cells or their combination. Generally, the basic cell of the ASIC is composed of one or more complementary MOSFETs (i.e., CMOS) with a view to increasing the integration and reducing the power consumption. The wiring lines between the individual complementary MOSFETs of the basic cells and between the circuits composed of the basic cells are made mainly of aluminum. These wiring lines themselves are automatically laid out by the DA (as abbreviated from Design Automation) system using a computer.
The aforementioned buffer circuit is composed of buffer circuit cells having a plurality of MOSFETs and is constructed by wiring the individual MOSFETs of the buffer circuit cells like the basic cells.
The aforementioned ASIC is constructed such that each of the input buffer circuits of the internal circuit and the buffer circuit is composed mainly of the complementary MOSFETS. On the other hand, the output buffer circuit of the buffer circuit is composed of a push-pull circuit. This push-pull circuit is arranged by connecting two n-channel MOSFETs in series between a reference supply voltage and an operating supply voltage. The reference supply voltage is set to 0 V, acting as the earth potential of the circuit, in a case in which a system having the ASIC incorporated thereinto uses a single supply voltage of 5 V.
The aforementioned push-pull circuit is featured by a high latch-up withstand voltage because it does not constitute a parasitic thyristor unlike the complementary MOSFET. Moreover, the push-pull circuit has such a high latch-up withstand voltage, as described above, that it can reduce the pitch between the individual MOSFETs to reduce the area to be occupied to an extent corresponding to the reduction of the pitch. In other words, the push-pull circuit is featured in that it can reduce the area to be occupied by the output buffer circuit thereby t improve the degree of integration of the ASIC. Since, however, the push-pull circuit experiences a voltage drop corresponding to the threshold voltage of the n-channel MOSFET, its output voltage takes a value which is calculated by subtracting the threshold voltage of the n-channel MOSFET from the supply potential.
On the other hand, the aforementioned ASIC is used in various applications for packaging a CPU or aiding the CPU of an external device as the degree of integration becomes greater or the multiple terminals progresses to a higher requirement. The ASI to be used for such application is arranged with a bus which is composed of a number of signal wiring lines for transmitting data between the circuits. As a result, the ASIC outputs a number of data such as 32 bits or 64 bits simultaneously via the bus line from the output buffer circuits. At the same time, the numerous data are simultaneously inputted from the external devices via the input buffer circuits.
In a case in which the aforementioned ASIC is packaged in the PGA structure, for example, and incorporated into the system, noises result in the supply voltages to be fed to the individual output buffer circuits, if the numerous output buffers are simultaneously operated. Such noises produce the phenomena in which the supply voltages to be instantly supplied to the output buffer circuits fluctuate on the basis of the inductance or resistance components specific to the supply voltage wiring lines (of aluminum) for supplying the supply voltages to the output buffer circuits, the wires in the package, and the external pins. On the other hand, the aforementioned noises are not intrinsic to the case in which the ASIC is packaged in the PGA structure but may occur in the case of a package of another structure. The noises produced in the aforementioned supply voltages would result in malfunctions in the internal circuits, such as loss of stored data of a flip-flop circuit when the supply voltage to be supplied to the flip-flop circuit of the internal circuit is common to that to be supplied to the output buffer circuit.
As counter-measures for such noises, it is effective to separate and isolate the supply voltage (e.g., the reference supply voltage and the operating supply voltage) to be supplied to the internal circuit of the ASIC and the supply voltage to be supplied to the buffer circuit. These supply voltages separated from each other are shared outside of the ASIC, i.e., in the system to be packaged with the ASIC.